1. Technical Field of the Invention
The invention relates generally to semiconductor-on-insulator devices and methods for forming the same. The invention relates particularly to semiconductor-on-insulator devices and methods for forming which avoid or reduce floating body effects.
2. Description of the Related Art
Silicon on insulator (SOI) materials offer potential advantages over bulk materials for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and eliminate latch-up in CMOS circuits. Compared to bulk circuits, SOI is more resistant to radiation. For example, silicon-on-sapphire (SOS) technology has been successfully used for years to fabricate radiation-hardened CMOS circuits for military applications. Circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of these devices are xe2x80x9cfloatingxe2x80x9d). However, partially-depleted metal oxide semiconductor field effect transistors (MOSFETs) on SOI materials typically exhibit parasitic effects due to the presence of the floating body (xe2x80x9cfloating body effectsxe2x80x9d). The partially-depleted devices are such that the maximum depletion width in the body is smaller than the thickness of the semiconductor Si layer, and a quasi-neutral region results which has a floating potential. These floating body effects may result in undesirable performance in SOI devices.
It will be appreciated from the foregoing that a need exists for SOI MOSFETs having reduced floating body effects.
A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. An electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.
According to an aspect of the invention, a semiconductor device includes a semiconductor layer with source and body regions of different conductivity, the semiconductor layer having an electrically-conducting region which overlaps the source and body regions.
According to another aspect of the invention, a semiconductor device includes a gate mounted on a layer of semiconductor material, the semiconductor material having a source region and a drain region which are symmetric with one another about the gate, and having a pair of electrically-conducting regions on opposite sides of the gate, the electrically-conducting regions being asymmetric with one another about the gate.
According to yet another aspect of the invention, a semiconductor device includes a gate mounted on a layer of semiconductor material, the semiconductor material having a source region and a drain region which are asymmetric with one another about the gate, and having a pair of electrically-conducting regions on opposite sides of the gate, the electrically-conducting regions being symmetric with one another about the gate.
According to still another aspect of the invention, a semiconductor device includes a gate mounted on a silicon-on-insulator wafer, the wafer including suicide regions on opposite sides of the gate which are asymmetric with one another about the gate.
According to a further aspect of the invention, a semiconductor device includes a gate mounted on a layer of semiconductor material, the semiconductor material having a source region and a drain region which are asymmetric with one another about the gate.
According to a still further aspect of the invention, a method of forming a semiconductor device includes using angled implanting to form a portion of a source region and a portion of a drain region which are asymmetric with one another about a gate.
According to another aspect of the invention, a method of forming a semiconductor device includes using partial masking of a surface of the device in forming a source region and a drain region which are asymmetric with one another about a gate.
According to yet another aspect of the invention, a method of forming a semiconductor device includes using spacers on opposite sides of a gate which are asymmetric with one another about the gate, to form semiconductor-metal compound regions on opposite sides of the gate which are asymmetric with one another.
According to still another aspect of the invention, a semiconductor device includes a semiconductor layer having source, drain, and body regions which are operatively coupled together, and an electrically-conducting region within the source and body regions, the electrically-conducting region electrically coupling the source region and the body region.
According to a further aspect of the invention, a method of forming a semiconductor device includes the steps of forming source, drain, and body regions in a semiconductor layer, and forming an electrically-conducting region including part of the source region and part of the body region, the electrically-conducting region electrically coupling the source region and the body region.
According to a still further aspect of the invention, a semiconductor device includes a semiconductor layer having a pair of adjacent regions of opposite conductivity, and an electrically-conducting region overlapping and electrically coupling the adjacent regions.
According to another aspect of the invention, a semiconductor device includes a semiconductor layer having source, drain, and body regions; a gate on the semiconductor layer, the gate operatively coupled to the source, drain, and body regions; and a pair of electrically-conducting regions on respective opposite sides of the gate, the electrically-conducting regions being substantially symmetric with one another about the gate; wherein one of the electrically-conducting regions electrically couples the source region and the body region.
According to yet another aspect of the invention, a method of forming a semiconductor device includes the steps of forming source, drain, and body regions in a semiconductor layer; forming a gate on the semiconductor layer before, during, or after the forming source, drain, and body regions; and forming a source-body electrically-conducting region including part of the source region and part of the body region, the electrically-conducting region electrically coupling the source region and the body region, and a drain electrically-conducting region; wherein the electrically-conducting regions are substantially symmetric about the gate.
According to still another aspect of the invention, a semiconductor device includes a semiconductor layer having source, drain, and body regions; a gate operatively coupled to the source, drain, and body regions; and an electrically-conducting region within the source and body regions, the electrically-conducting region electrically coupling the source region and the body region; wherein the source region is substantially symmetric to the drain region about the gate.
According to a further aspect of the invention, a method of forming a semiconductor device includes the steps of forming source, drain, and body regions in a semiconductor layer; forming a gate on the semiconductor layer before, during, or after the forming source, drain, and body regions; and forming an electrically-conducting region including part of the source region and part of the body region, the electrically-conducting region electrically coupling the source region and the body region; wherein the source and drain regions are substantially symmetric about the gate.
According to a still further aspect of the invention, a semiconductor device comprising a semiconductor layer and a gate on the semiconductor layer, wherein the semiconductor layer includes a pair of electrically-conducting regions on opposite sides of the gate, the electrically-conducting regions being asymmetric with one another about the gate.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.